rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit 25 msps a/d converter AD9032 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram analog input encode 5 8 12 track- and- hold sum amp flash adc/dac error corr. logic residue encoder digital output data ready timing circuits AD9032 features 25.6 msps conversion speeds on-board t/h, references, timing low power: 3.8 w single 40-pin package 74 db spurious-free dynamic range to 12 mhz a in bipolar input: 6 1.024 v applications radar signal intelligence digital spectrum analyzers medical imaging electro-optics evaluation board an evaluation board which is available for the AD9032 (part number ad9034/pcb) provides an easy and flexible method for evaluating the adcs performance without (or prior to) developing a user-specified printed circuit board. the evalua- tion board was originally designed and used for evaluating the ad9034 a/d converter, but is equally useful for the pin- compatible a d9032. the board includes a reconstruction dac, analog input ampli- fier, and digital output interface. physically, it is 7.25 inches 3 6 inches in size and uses the layout and applications information contained in the ad9034 data sheet. generous space is provided near the analog input and digital outputs of the evaluation board to support additional signal pro- cessing components the user may wish to add. these two proto- typing areas include through holes with 100-mil centers to support a variety of component additions. for additional operating details, a schematic of the evaluation board, and complete layout information, consult the data sheet on the ad9034 a/d converter. general description the AD9032 is the worlds fastest 12-bit analog-to-digital con- verter (adc) that includes on-board t/h, voltage references, and timing circuits. the AD9032 uses a subranging converter architecture to achieve sample rates from dc to 25.6 msps. pack- aged in a single 40-pin hybrid, the AD9032 is pin-compatible with the ad9034, which operates at word rates up to 20 msps. this ecl-compatible adc requires only +5 v and C5.2 v sup- plies, an analog input, and a stable ecl clock to obtain the best dynamic performance available in a 12-bit adc. this kind of performance is achieved with advanced bipolar circuits, custom designed and manufactured by analog devices. the latest in monolithic track-and-hold technology ensures accurate sam- pling of high frequency analog inputs. dynamic performance has been optimized to achieve snr of 64 db and a spurious-free dynamic range (sfdr) of 74 db for analog bandwidths up to 12 mhz. all units are tested for dy- namic performance at a sample rate of 25.6 msps. the AD9032 is available in either a 40-pin ceramic dip or leaded flatpack. the two versions operate over an industrial (C25 c to +85 c) or military (C55 c to +125 c) temperature range.
AD9032Cspecifications electrical characteristics test AD9032ad/az AD9032bd/bz AD9032td/tz parameter (conditions) temp level min typ max min typ max min typ max units resolution 12 12 12 bits dc accuracy differential nonlinearity +25 c i 0.65 1.25 0.5 1.0 0.5 1.0 lsb full vi 1.75 1.5 1.5 lsb integral nonlinearity +25 c v 1.0 1.0 1.0 lsb full v 2.0 2.0 2.0 lsb no missing codes full vi guaranteed guaranteed guaranteed offset error +25 ci 515 515 515mv full vi 25 25 30 mv gain error +25 ci 0.5 1.0 0.5 1.0 0.5 1.0 % fs full vi 2.5 2.5 2.5 % fs analog input input voltage range +25 ci 1.024 1.024 1.024 v input resistance +25 c vi 95 100 105 95 100 105 95 100 105 w input capacitance +25 c iv 7 10 7 10 7 10 pf analog bandwidth +25 c iv 150 220 150 220 150 220 mhz switching performance 1 conversion rate full vi dc 25.6 dc 25.6 dc 25.6 msps aperture delay (t a ) full iv 1 3 5 1 3 5 1 3 5 ns aperture uncertainty (jitter) full iv 4 8 4 8 4 8 ps, rms output delay (t od ) full iv 9 13 17 9 13 17 9 13 17 ns data ready delay (t dr ) full iv 3.5 7.5 10.5 3.5 7.5 10.5 3.5 7.5 10.5 ns output time skew full iv 1 2 1 2 1 2 ns encode input logic 1 voltage full iv C1.1 C1.1 C1.1 v logic 0 voltage full iv C1.5 C1.5 C1.5 v logic 1 current full vi 150 300 150 300 150 300 m a logic 0 current full vi 150 300 150 300 150 300 m a input capacitance +25 c v 10 10 10 pf pulse width (high) +25 civ10 1010ns pulse width (low) +25 civ10 1010ns dynamic performance transient response +25 civ 1227 1227 1227ns overvoltage recovery time +25 civ 2537 2537 2537ns harmonic distortion analog input @ 1.2 mhz +25 c i 70 80 75 82 75 82 dbc @ 1.2 mhz full vi 67 70 70 dbc @ 4.3 mhz +25 c v 76 77 77 dbc @ 9.6 mhz +25 c i 68 75 72 76 72 76 dbc @ 9.6 mhz full vi 64 68 64 dbc @ 12.1 mhz +25 c v 72 74 74 dbc signal-to-noise ratio 2 analog input @ 1.2 mhz +25 c i 63 66 64 67 64 67 db @ 1.2 mhz full vi 61 63 61 db @ 4.3 mhz +25 c v 64 65 65 db @ 9.6 mhz +25 c i 62 64 62 64 62 64 db @ 9.6 mhz full vi 60 61 58 db @ 12.1 mhz +25 c v 64 64 64 db two-tone intermodulation distortion rejection 3 +25 c v 66 68 68 dbc C2C (+v s = +5 v; Cv s = C5.2 v, encode = 25.6 msps, unless otherwise noted) rev. 0
test AD9032ad/az AD9032bd/bz AD9032td/tz parameter (conditions) temp level min typ max min typ max min typ max units digital outputs (10k ecl) logic 1 voltage full vi C1.1 C1.1 C1.1 v logic 0 voltage full vi C1.5 C1.5 C1.5 v output coding 2s complement 2s complement 2s complement power supply +v s supply voltage full vi 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 ma +v s supply current full vi 133 160 133 160 133 160 ma Cv s supply voltage full vi C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 ma Cv s supply current full vi 610 672 610 672 610 672 ma power dissipation full vi 3.8 4.5 3.8 4.5 3.8 4.5 w power supply rejection ratio (psrr) 4 full vi 4.0 10 4.0 10 4.0 10 mv/v notes 1 outputs terminated through 510 w to C5.2 v; c l < 4 pf. typical values are valid for +25 c ambient. 2 rms signal to rms noise with analog input signal 1 db below full scale at specified frequency. 3 intermodulation measured with analog input frequencies of 9.3 mhz and 9.6 mhz at 7 db below full scale. 4 psrr is sensitivity of offset error to power supply variations within the 5% limits shown. specifications subject to change without notice. absolute maximum ratings 1 +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 v Cv s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C7 v analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to +v s digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to 0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature range AD9032ad/bd/az/bz . . . . . . . . . . . . . . . . C25 c to +85 c AD9032td/tz . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c maximum junction temperature 2 +175 c lead temperature (soldering, 10 seconds) . . . . . . . . . +300 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances: q ca = 13 c/w; t j C t c = 10 c max (worst case die junction temperature rise). see thermal management section. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. devices are 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/ industrial devices. ordering guide model temperature range package description package option AD9032ad C25 c to +85 c 40-pin ceramic dip dh-40a AD9032az* C25 c to +85 c 40-pin ceramic leaded chip carrier z-40 AD9032bd C25 c to +85 c 40-pin ceramic dip dh-40a AD9032bz* C25 c to +85 c 40-pin ceramic leaded chip carrier z-40 AD9032td C55 c to +125 c 40-pin ceramic dip dh-40a AD9032tz* C55 c to +125 c 40-pin ceramic leaded chip carrier z-40 ad9034/pwb printed circuit board (only) of evaluation circuit ad9034/pcb complete evaluation board, assembled and tested (order AD9032 dip separately) *ceramic leaded chip carrier packages are tested and shipped with unformed leads. consult the factory for availability. AD9032 rev. 0 C3C
AD9032 rev. 0 C4C definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is re- duced by 3 db. aperture delay (t a ) the delay between the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. data ready delay (t dr ) the delay between the 50% point of the change in output data and the 50% point of the rising edge of data ready. differential nonlinearity (dnl) the deviation of any code width from an ideal 1 lsb step, as determined by a histogram. harmonic distortion the rms value of the fundamental divided by the rms value of the worst harmonic. integral nonlinearity (inl) the deviation of the transfer function from a reference line mea- sured in fractions of 1 lsb using a best straight line deter- mined by a least square curve fit, as determined by a histogram. output delay (t od ) the delay between the 50% point of the rising edge of the encode command and the 50% point of the next change in output data. output time skew bit-to-bit time variations among d 0 to d 11 outputs. time skew includes high-to-low and low-to-high transitions of the digital output bits. overvoltage recovery time the amount of time required for the converter to recover to 12-bit accuracy after an analog input signal 150% of full scale is reduced to the midscale of the converter. power supply rejection ratio the ratio of a change in power supply voltage which results in a change in input offset voltage. pulse width (high and low) rated performance of the adc is assured when stated restric- tions on encode pulse width shown in specifications table are observed. signal-to-noise ratio (snr) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral compo- nents, including harmonics but excluding dc, with an analog in- put signal 1 db below full scale. spurious free dynamic range (sfdr) the rms value of the fundamental divided by the rms value of the highest spurious signal. this is generally specified as a func- tion of input signal level. transient response the time required for the converter to achieve 12-bit accuracy when a full-scale step function is applied to the analog input. two-tone intermodulation distortion (imd) rejection the ratio of the power of either of two input signals to the power of the strongest third-order imd signal. n n + 1 n ?2 n ?1 encode data output n analog in t/h hold data ready track t a t a = 3ns typical t od t od = 13ns typical t dr t dr = 7.5ns typical timing diagram
AD9032 rev. 0 C5C pin descriptions pin name description 1 gain can be used to null out initial gain adjust error of adc. normally open. 2 offset can be used to null out initial off- adjust set error of adc. normally open. 3, 5, 6, ground all ground pins should be connect 14, 21, ed together and to low-impedance 22, 35, 40 ground plane near ad9034. 4 analog analog input to adc, 1.024 v input input range; 100 w input resist- ance; 7 pf input capacitance. 7, 8, 9, 15, dnc do not connect. internal test 16, 36, 37 points. 10 overflow ecl-compatible output; normally low. high when analog input > +fs. 11 data ecl-compatible output. rising ready edge of signal suitable, for exter- nally latching d 0 C d 11 . 12, 17, Cv s C5.2 v supply voltage. 20, 38 13, 39 +v s +5.0 v supply voltage. 18 encode differential ecl convert command. 19 encode sampling occurs on rising edge; no internal terminations. 23C34 d 0 Cd 11 ecl-compatible digital outputs; 2s complement coding. theory of operation the AD9032 is a digitally corrected subranging analog-to-digital converter (adc) optimized for fast sampling rates and dynamic range. refer to the block diagram on the first page. the AD9032 is a vertically integrated structure consisting of a track- and-hold (t/h) amplifier, a combined flash adc and digital-to- analog (dac), a summation amplifier, digital error correction logic, and timing circuits. reference circuits to generate stable dc voltages and currents that maintain the static accuracy of the device are also included, but are not shown on the block diagram. internally, the monolithic t/h (ad9101) provides fast settling and acquisition times while minimizing distortion introduced by the sampling process. the unique design of the sampling bridge allows accurate sampling of high slew rate signals with negligible distortion. the effects of jitter and other aperture errors have been reduced to provide dynamic performance previously un- available in monolithic and discrete designs. at the output of the t/h amplifier, the analog input is converted by the first (5-bit) adc. this 12-bit representation of the input value is stored in the digital error correction logic. it is also con- verted back to an analog signal by the 14-bit-accurate dac on the same chip with the adc. the 32 dac current sources are steered directly by the outputs of the 32 input comparators on the 5-bit adc. this minimizes propagation delay through the dac, and allows the summation of the dac signal and the held output of the t/h to settle quickly. the hold time of the t/h is optimized to allow sufficient settling time without sacrificing the acquisition time necessary to acquire the next sample. the residue signal, representing the difference between the 5-bit conversion (dac output) and the input signal held by the t/h, is amplified by the summation amplifier. during the tracking pe- riod of the t/h, this residue signal can be much larger than the input range of the 8-bit adc and would saturate the output stage of a normal amplifier. to protect the adc and maintain fast settling times under all conditions, the summation amplifier is a custom design with clamping circuits that prevent satura- tion, limit the output voltage, and preserve settling time. the 8-bit flash adc determines the 7 least significant bits (lsbs) of the 12-bit conversion and generates a correction bit for any small errors created by inaccuracies in the first 5-bit con- version. this 8-bit signal and the 5-bit quantization are com- bined to obtain a 12-bit-accurate representation of the analog input voltage. pin designations ground +v s ? s dnc dnc ground d 0 (lsb) d 1 d 5 d 6 d 7 d 8 d 9 d 10 d 11 (msb) ground ground dnc dnc ground analog input ground ground dnc dnc overflow data ready ? s +v s ground dnc dnc ? s dnc encode ? s digital encode 140 5 10 15 20 21 26 31 36 16 17 18 19 22 23 24 25 27 28 29 30 32 33 34 35 37 38 39 2 3 4 6 7 8 9 11 12 13 14 top view (not to scale) AD9032 d 2 d 3 d 4
AD9032 rev. 0 C6C using the AD9032 layout information preserving the accuracy and dynamic performance of the AD9032 requires that designers pay special attention to the lay- out of the printed circuit board. signal paths should be imped- ance matched and properly terminated at or near the package connections. analog signal paths should be isolated from digital signal paths. capacitive and inductive coupling of digital signals into analog signal sections can degrade the overall performance of the a/d converter. analog input the analog input pin of the AD9032 is terminated with a 100 w load. the analog input range of the AD9032 is factory trimmed for a 1.024 v input for compatibility with the ad9034. the signal presented to the monolithic t/h is divided in half to opti- mize dynamic performance. when the amplitude, bandwidth, or dc level of the analog input requires external signal conditioning, the selection of the input amplifier is of particular concern. the noise and distortion of the amplifier must be taken into account to preserve the dy- namic range of the AD9032. the ad9617 wideband, current feedback amplifier is an excellent choice for most applications. timing internal timing for the AD9032 is trimmed at the factory to sim- plify use. care should be taken to ensure that the encode com- mand to the AD9032 is free from jitter that can degrade dynamic performance. differential ecl inputs to the AD9032 can be derived from a single-ended source using a fast compara- tor such as the ad96685. the encode source should be located and terminated as close to the AD9032 as possible. the ecl-compatible digital outputs are latched to provide valid data for the entire conversion period (less the transition region of latch). this data should be latched into external ecl regis- ters located near the AD9032. external termination resistors are required (510 w recommended). the data are latched with ei- ther the encode command or the data ready signal provided on the AD9032. the rising edge of the data ready signal occurs typically 7.5 ns after the data changes. gain and offset adjustment gain and offset pins are normally not connected. rated perfor- mance is guaranteed without any external connection to these pins. in most applications, wide variations in input signal range and offset can be accommodated using external amplifiers. however, in those applications where a vernier adjustment is re- quired (such as nulling out factory trim limits), the gain and off- set pins will provide sufficient adjustment range. both inputs offer a 20 k w input resistance that can be driven from a voltage source (dac, amplifier) or the center tap of a potentiometer. the offset pin provides a 195 mv/v sensitivity to input offset, while the gain pin offers 120 mv/v adjustment of the full-scale input range of the adc. the adjustment range for offset is limited to 10 mv and for gain is 20 mv without intro- ducing potential dynamic errors or restricting the operating tem- perature range of the part. power supplies the unique design of the AD9032 provides excellent dynamic performance without a need for high voltage power supplies. two supplies (+5 v and C5.2 v) are all that are required to achieve rated performance. careful layout and decoupling of power supplies used in conjunction with a low impedance ana- log ground plane will reduce supply-related noise components. separate analog and digital supplies are not required. in applica- tions with only limited analog supply current, a separate digital supply source can be used for the C5.2 v supply on pin 20. this supply typically requires 310 ma (330 ma max) and may be shared with other ecl logic devices when isolated with bypass capacitors and/or ferrite bead inductors (fair-rite products corporation part # 2743001111, wallkill, ny). each power supply pin should be capacitively decoupled to the ground plane through a good high frequency ceramic capacitor (0.1 m f) and a single large value capacitor (tantalum 10 m f). for optimum performance, clean linear supplies ensure that switching noise on the supplies does not introduce distortion products during the encoding process. recognizing, however, that switching power supplies may be required in power- sensitive applications, decoupling recommendations outlined above are critically important for using switching supplies effectively. elsewhere in this data sheet, a graph shows the psrr of the AD9032 as a function of the ripple frequency present on the AD9032 supplies. clearly, if they must be used, switching power supplies with the lowest possible frequency should be selected. thermal management the AD9032 design minimizes power dissipation; however, the adc does typically require 3.8 w (4.5 w max) to operate. to ensure long life and reliable operation, the maximum junction temperature in the AD9032 must be limited to +175 c. within the hybrid, the hottest discrete die has a case to junction temperature rise of 10 c (max). therefore, the case tempera- ture of the AD9032 should not exceed +165 c under worst case operating conditions. without airflow, the q ca of the hybrid package is 13 c/w. assuming maximum power dissipation, this causes a 57 c rise in case temperature over the ambient air tem- perature. the maximum still air temperature, therefore, is equal to +108 c. rated performance of the AD9032 is guaranteed for case oper- ating temperatures of +85 c (AD9032a/b) and +125 c (AD9032t). this equates to a maximum operating ambient temperature of +28 c and +68 c, respectively, in still air. in most applications, airflow is recommended. the following im- provements in the thermal characteristics of the system assume that the AD9032 is soldered to a pc board. the q ca of the hybrid is reduced to 5 c/w with 500 lfpm air- flow. this will extend the rated performance to ambient operat- ing ranges of +63 c for the AD9032a/b and +103 c for the AD9032t. the addition of a heat sink (thermalloy #6087b, dallas, texas; phone 214-243-0839) will further improve the thermal transfer of the hybrid to 3 c/w (@ 500 lfpm). using a heat sink with airflow, the total case to ambient temperature rise is only 13 c, which results in a maximum ambient environ- ment of +72 c (AD9032a/b) and +112 c (AD9032t).
AD9032 rev. 0 C7C 0 ?00 12.8 ?3 dc ?0 ?7 ?3 ?7 10.2 7.7 5.1 2.6 frequency ?mhz output ?db encode = 25.6 mhz freq = 12.1 mhz snr = 64.1 db sfdr = 75.2 dbfs fund = ?.0 dbfs 2nd harm = ?4.4 dbc 3rd harm = ?2.1 dbc 9 5 7 9 8 6 4 2 AD9032 a/d converter fft 90 60 30 1 10 100 40 50 70 80 signal-to-noise ratio ?db input frequency ?mhz word rate = 25.6 msps +25 c ?5 c +125 c AD9032 snr vs. analog input 0 ?00 12.8 ?3 dc ?0 ?7 ?3 ?7 10.2 7.7 5.1 2.6 9 8 7 6 5 4 3 2 frequency ?mhz output ?db encode = 25.6 mhz freq = 1.2 mhz snr = 66.7 db sfdr = 84.8 dbfs fund = ?.0 dbfs 2nd harm = ?0.3 dbc 3rd harm = ?9.3 dbc AD9032 a/d converter fft 90 60 30 1 10 100 40 50 70 80 harmonic distortion ?db input frequency ?mhz +25 c ?5 c +125 c word rate = 25.6 msps AD9032 harmonic distortion vs. analog input 50 35 20 0.1 1 10 25 30 40 45 supply ripple frequency ?mhz word rate = 25.6 msps +25 c power supply rejection ratio ?db psrr = 20 x log ( ) supply ripple equiv. input ripple AD9032 psrr vs. supply ripple frequency 2.5k 2.5k 2.5k encode encode +v s 200 m a equivalent encode input circuit ? s +v s 1ma 50 50 a in 1ma equivalent analog input circuit d 0 ?d 11 equivalent digital output circuit
AD9032 rev. 0 C8C outline dimensions dimensions shown in inches and (mm). dh-40a 40-lead bottom brazed ceramic dip pin 1 identifier 1.900 0.008 (48.26 0.203) 0.018 0.002 (0.457 0.051) 0.100 0.005 (2.54 0.127) 0.040 (1.02) typ 0.225 (5.715) max 0.035 0.010 (0.889 0.254) 0.180 (4.57) min 0.010 0.002 (0.254 0.051) 0.200 (5.080) 0.120 (3.048) seating plane 2.095 0.021 (53.21 0.533) 1.090 0.011 (27.69 0.279) 0.900 0.010 (22.86 0.254) z-40 40-lead leaded flatpack 0.010 0.002 (0.254 0.051) 0.350 (9.89) typ 0.205 (5.21) max 2.095 0.021 (53.21 0.533) 1.090 0.011 (27.69 0.279) 0.018 0.002 (0.457 0.051) 0.100 0.005 (2.54 0.127) pin 1 identifier 1.900 0.008 (48.26 0.203) at braze 0.123 (3.12) max c1690C24C8/92 printed in u.s.a.
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